1. Field of the Invention
The present invention relates to a memory module selection and reconfiguration apparatus in a data processing system.
2. Description of the Prior Art
Most data processing systems presently used provide the opportunity for increasing the capacity of the working memory in order to fulfill new requirements.
This is commonly attained by arranging the working memory modularly; i.e., by having a variable number of identical memory modules housed into a unit which is designed to contain a certain maximum number of modules. A memory module has a predetermined capacity (for instance 128K bytes) and is implemented with printed circuit boards of predetermined sizes and by a denoted number of standard integrated memory components.
Because of rapid changes in technology, the manufacturers of data processing systems are faced with the problem of upgrading the working memory at minimum cost. Because of such progress in new integrated memory components which have greater and greater capacity, a memory module may be built which has a greater capacity than it had (for instance double or quadruple) while at the same time maintaining the size of its memory board unchanged. Thus the capacity of a working memory may be increased not only by increasing the number of memory modules, but also by utilizing memory modules of greater capacity. Moreover it is unnecessary to remove the fewer capacity modules already installed. In such a way it is possible to obtain a working memory with a capacity variable as a function of the number and type of modules, and in which modules of different capacity are present at the same time. However there is a problem in addressing such memories. Prearranged circuits are required that can address any of the several modules of the working memory so that the several modules may be addressed as if they constituted an addressable continuous space of one memory only.
Because in data processing systems processors, working memories and peripheral units are all interconnected via busses which define a common interface for several types of equipments, it is not possible to perform the required address conversion outside the working memory without affecting the interfaces of all the equipment. Such conversion must therefore occur within the working memory and must be performed with simple and fast circuits so as not to introduce unacceptable delays in the memory access times and further increase the complexity and the related cost of such circuits. A partial solution to this problem is described in U.S. Pat. No. 4,001,786. According to the mentioned patent a memory unit comprises an ordered plurality of memory modules with each module including a module selector which receives at its inputs a suitable part of the memory addresses in the form of signals representative of the capacity of the related module and other signals representative of the sum of the capacities of the modules preceding the considered module. Referring to each module, the related selector comprises a network for summing the capacities of the preceding modules, a register for storing such sum, a network for subtracting the sum contained in such register to the received memory address part, a comparison network for determining if the sign of the subtraction operation is positive, negative or null and, a function of the result, for enabling the selection of the related module. The proposed solution is partial because it requires a great number of components and therefore is complex and expensive. Additionally the selection of a memory module is conditioned on the joint occurrence of two conditions; i.e., that the address has to be greater than the capacity of the modules preceding the considered one and lesser than the memory capacity given by the sum of the capacity of the preceding modules and by the capacity of the considered module. This requires the execution of a logic AND operation involving a certain delay time which, however short, cannot be avoided and is due to the signal propagation time in the logical circuits. The above mentioned comparison system utilizing first a subtraction operation and then a comparison operation, is relatively slow. Add this disadvantage to the complexity of hardware components that the system requires and we have an inefficient apparatus.